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stk22c48 16-kbit (2 k 8) autostore? nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-51000 rev. *e revised february 23, 2012 16 features 25 ns and 45 ns access times hands off automatic store on power-down with external 68 f capacitor store to quantumtrap? nonvolatile elements is initiated by software, hardware, or autostore? on power-down recall to sram initiated by software or power-up unlimited read, write, and recall cycles 1,000,000 store cycl es to quantumtrap 100 year data retention to quantumtrap single 5 v + 10% operation commercial and industrial temperatures 28-pin 300 mil and (330 mil) sm all outline integrated circuit (soic) package restriction of hazardous substances (rohs) compliant functional description the cypress stk22c48 is a fast static ram with a nonvolatile element in each memory cell. the embedded nonvolatile elements incorporate quantumtrap technology producing the world?s most reliable nonvolatile memory. the sram provides unlimited read and write cycles , while independent nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power-down. on power-up, data is restored to the sram (the recall operation) from the nonvolatile memory. a hardware store is initiated with the hsb pin. store/ recall control power control static ram array 32 x 512 quantum trap 32 x 512 store recall column i/o column dec row decoder input buffers oe ce we hsb v cc v cap a 0 a 1 a 2 a 3 a 4 a 10 a 5 a 6 a 7 a 8 a 9 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 logic block diagram not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 2 of 17 contents pin configurations ........................................................... 3 device operation .............................................................. 4 sram read ....................................................................... 4 sram write ....................................................................... 4 autostore operation ........................................................ 4 autostore inhibit mode .................................................... 4 hardware store (hsb) operation ................................. 5 hardware recall (power up) ........................................ 5 data protection ................................................................. 5 noise considerations....................................................... 5 hardware protect.............................................................. 5 low average active power.............................................. 5 preventing store............................................................... 6 best practices................................................................... 6 maximum ratings ............................................................. 7 operating range ............................................................... 7 dc electrical characteristics .......................................... 7 data retention and endurance ....................................... 7 capacitance ...................................................................... 8 thermal resistance .......................................................... 8 ac test conditions .......................................................... 8 ac switching characteristics ... ...................................... 9 sram read cycle ...................................................... 9 switching waveforms ...................................................... 9 sram write cycle ..................................................... 10 autostore or power up recall .................................. 11 switching waveform ...................................................... 11 hardware store cycle ................................................. 12 switching waveform ...................................................... 12 ordering information ...................................................... 13 ordering code definitions ..... .................................... 13 package diagrams .......................................................... 14 document conventions ................................................. 15 acronyms ................................................................. 15 units of measure ....................................................... 15 document history page ................................................. 16 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc solutions ......................................................... 17 not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 3 of 17 pin configurations figure 1. pin diagram - 28-pin soic table 1. pin definitions pin name alt io type description a 0 ?a 10 input address inputs. used to select one of the 2, 048 bytes of the nvsram. dq 0 ?dq 7 input or output bidirectional data io lines . used as input or output lines depending on operation. we w input write enable input, active low . when the chip is enabled and we is low, data on the io pins is written to the specific address location. ce e input chip enable input, active low . when low, selects the chip. when high, dese lects the chip. oe g input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the io pins to tri-state. v ss ground ground for the device . the device is connected to ground of the system. v cc power supply power supply inputs to the device . hsb input or output hardware store busy (hsb ) . when low, this output indicates a hardware store is in progress. when pulled low external to the chip, it initiate s a nonvolatile store operation. a weak internal pull-up resistor keeps this pin high if not connected (connection optional). v cap power supply autostore capacitor . supplies power to nvsram during power loss to store data from sram to nonvolatile elements. nc no connect no connect . this pin is not connected to the die. v cap a 7 a 6 a 5 a 4 v cc hsb we a 8 a 9 oe a 10 dq6 dq7 dq5 ce dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v ss dq0 a 3 a 2 a 1 a 0 dq1 dq2 28-soic top view (not to scale) nc nc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 4 of 17 device operation the stk22c48 nvsram is made up of two functional components paired in the same physical cell. these are an sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferred to the nonvolatile cell (the store operation) or from the nonvolatile cell to sram (the recall operation). this unique arch itecture enables the storage and recall of all cells in parallel. during the store and recall operations, sram read and write operations are inhibited. the stk22c48 supports unlimited re ads and writes similar to a typical sram. in addition, it provides unlimited recall operations from the nonvolatile cells and up to one million store operations. sram read the stk22c48 performs a read cycle whenever ce and oe are low while we and hsb are high. the address specified on pins a 0?10 determines the 2,048 data bytes accessed. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data outputs repeatedly respond to address changes within the t aa access time without the need for transitions on any control input pins, and remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed whenever ce and we are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must rema in stable until either ce or we goes high at the en d of the cycle. the dat a on the common i/o pins dq 0?7 are written into the me mory if it has valid t sd , before the end of a we controlled write or before the end of an ce controlled write. keep oe high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation during normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. figure 2 shows the proper connectio n of the storage capacitor (v cap ) for automatic store operation. a charge storage capacitor between 68 f and 220 f (+ 20%) rated at 6 v should be in system power mode, both v cc and v cap are connected to the +5 v power supply without the 68 ? f capacitor. in this mode, the autostore function of the stk2 2c48 operates on the stored system charge as power goes do wn. the user must, however, guarantee that v cc does not drop below 3.6 v during the 10 ms store cycle. to prevent unneeded store operations, automatic stores and those initiated by externally driving hsb low are ignored, unless at least one write operation takes place since the most recent store or recall cycle. an optional pull-up resistor is shown connected to hsb . this is used to signal the system that the autostore cycle is in progress. autostore inhibit mode if an automatic store on power loss is not required, then v cc is tied to ground and +5 v is applied to v cap ( figure 3 on page 5 ). this is the autostore inhibit mode, where the autostore function is disabled. if the stk22c48 is operated in this config- uration, references to v cc are changed to v cap throughout this data sheet. in this mode, store operations are triggered with the hsb pin. it is not permissible to change between these three options ?on the fly?. figure 2. autostore mode vcc v cap mho k01 f 86 5 %02+ ,v6 mho k01 we hsb vss f 1.0 5 ssapyb not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 5 of 17 figure 3. autostore inhibit mode hardware store (hsb ) operation the stk22c48 provides the hsb pin for controlling and acknowledging the store operations. the hsb pin is used to request a hardware stor e cycle. when the hsb pin is driven low, the stk22c48 conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram takes place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition, while the store (initiated by any means) is in progress. pull-up this pin with an external 10 k ohm resistor to v cap if hsb is used as a driver. sram read and write operatio ns, that are in progress when hsb is driven low by any means, are given time to complete before the store operation is initiated. after hsb goes low, the stk22c48 continues sram operations for t delay . during t delay , multiple sram read operations take place. if a write is in progress when hsb is pulled low, it allows a time, t delay to complete. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. during any store operation, rega rdless of how it is initiated, the stk22c48 continues to drive the hsb pin low, releasing it only when the store is complete. after completing the store operation, the stk22c48 remains disabled until the hsb pin returns high. if hsb is not used, it is left unconnected. hardware recall (power up) during power-up or after any low power condition (v cc < v reset ), an internal recall request is latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle is automatically initiated and takes t hrecall to complete. data protection the stk22c48 protects data from corruption during low voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc is less than v switch . if the stk22c48 is in a write mode (both ce and we are low) at power-up after a recall or after a store, the write is inhibited until a negative transition on ce or we is detected. this protects again st inadvertent writes during power-up or brown out conditions. noise considerations the stk22c48 is a high speed memory. it must have a high frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss, using leads and traces that are as short as possible. as with all high speed cmos ics, careful routing of power, ground, and signals reduce circuit noise. hardware protect the stk22c48 offers hardware protection against inadvertent store operation and sram writes during low voltage conditions. when v cap stk22c48 document number: 001-51000 rev. *e page 6 of 17 preventing store the store function is disabled by holding hsb high with a driver capable of sourcing 30 ma at a v oh of at least 2.2 v, because it must overpower the internal pull-down device. this device drives hsb low for 20 ns at the onset of a store. when the stk22c48 is connected for autostore operation (system v cc connected to v cc and a 68 ? f capacitor on v cap ) and v cc crosses v switch on the way down, the stk22c48 attempts to pull hsb low. if hsb does not actually get below v il , the part stops trying to pull hsb low and abort the store attempt. best practices nvsram products have been used effectively for over 15 years. while ease of use is one of th e product?s main system values, experience gained working with h undreds of applications has resulted in the following suggestions as best practices: the nonvolatile cells in an nvsram are programmed on the test floor during final test and quality assurance. incoming inspection routines at customer or contract manufacturer?s sites sometimes reprogram these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. the end product?s firmware should not assume that an nv array is in a set programmed state. routines that check memory content values to determine fi rst time system configuration, cold or warm boot status, and so on must always program a unique nv pattern (for example, complex 4-byte pattern of 46 e6 49 53 hex or more random by tes) as part of the final system manufacturing test to ensure these system routines work consistently. power-up boot firmware routines should rewrite the nvsram into the desired state. while the nvsram is shipped in a preset state, best practice is to again rewrite the nvsram into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on). the v cap value specified in this data sheet includes a minimum and a maximum value size. the best practice is to meet this requirement and not exceed the maximum v cap value because the higher inrush currents may reduce the reliability of the internal pass transistor. customers who want to use a larger v cap value to make sure there is extra store charge should discuss their v cap size selection with cypress. figure 4. current versus cycle time (read) figure 5. current versus cycle time (write) table 2. hardware mode selection ce we hsb a10?a0 mode i/o power h x h x not selected output high z standby l h h x read sram output data active [1] l l h x write sram input data active x x l x nonvolatile store output high z i cc2 [2] notes 1. i/o state assumes oe < v il . activation of nonvolatile cycles does not depend on state of oe . 2. hsb store operation occurs only if an sram write is done since the last nonvolatile cycle. after th e store (if any) completes, the part goes into standby mode, inhibiting all operations until hsb rises. not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 7 of 17 maximum ratings exceeding maximum ratings may s horten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ?c temperature under bias. ............ ............... ?55 ? c to +125 ?c supply voltage on v cc relative to v ss ............?0.5 v to 7.0 v voltage on input relative to v ss ........... ?0.6 v to v cc + 0.5 v voltage on dq 0-7 or hsb .................... ?0.5 v to v cc + 0.5 v power dissipation ........................................................ 1.0 w dc output current (1 output at a time, 1 s duration) .... 15 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 4.5 v to 5.5 v industrial ?40 ? c to +85 ? c 4.5 v to 5.5 v dc electrical characteristics over the operating range (v cc = 4.5 v to 5.5 v) [3] parameter description test conditions min max unit i cc1 average v cc current t rc = 25 ns t rc = 45 ns dependent on ou tput loading and cycle rate. values obtained without output loads. i out = 0 ma. commercial ? 85 65 ma ma industrial ? 90 65 ma ma i cc2 average v cc current during store all inputs do not care, v cc = max average current for duration t store ?3ma i cc3 average v cc current at t rc = 200 ns, 5 v, 25 c typical we > (v cc ? 0.2 v). all ot her inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. ?10ma i cc4 average v cap current during autostore cycle all inputs do not care, v cc = max average current for duration t store ?2ma i sb1 [4] average vcc current (standby, cycling ttl input levels) t rc = 25 ns, ce > v ih t rc = 45 ns, ce > v ih commercial ? 25 18 ma ma industrial ? 26 19 ma ma i sb2 [4] v cc standby current ce > (v cc ? 0.2 v). all others v in < 0.2 v or > (v cc ? 0.2 v). standby current level after n onvolatile cycle is complete. inputs are static. f = 0 mhz. ?1.5ma i ilk input leakage current v cc = max, v ss < v in < v cc ?1 +1 ? a i olk off state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih or we < v il ?5 +5 ? a v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?4 ma except hsb 2.4 ? v v ol output low voltage i out = 8 ma except hsb ?0.4v v bl logic ?0? voltage on hsb output i out = 3 ma ? 0.4 v v cap storage capacitor between v cap pin and vss, 6 v rated. 68 f ?10%, +20% nom. 61 220 f data retention and endurance parameter description min unit data r data retention 100 years nv c nonvolatile store operations 1,000 k notes 3. v cc reference levels throughout this data sheet refer to v cc if that is where the power s upply connection is made, or v cap if v cc is connected to ground. 4. ce > v ih does not produce standby current levels until any nonvolatile cycle in progress has timed out. not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 8 of 17 capacitance in the following table, the capacitance parameters are listed. [5] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 0 to 3.0 v 8pf c out output capacitance 7pf thermal resistance in the following table, the thermal resistance parameters are listed. [5] parameter description test conditions 28-soic (300 mil) 28-soic (330 mil) unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. tbd tbd ?c/w ? jc thermal resistance (junction to case) tbd tbd ?c/w figure 6. ac test loads ac test conditions 5.0 v output 30 pf r1 963 ? r2 512 ? 5.0 v output 5 pf r1 963 ? r2 512 ? for tri-state specs input pulse levels.................................................... 0 v to 3 v input rise and fall times (10% to 90%)......................... < 5 ns input and output timing referenc e levels .......... ............. 1.5 v note 5. these parameters are guaranteed by design and are not tested. not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 9 of 17 ac switching characteristics sram read cycle parameter description 25 ns 45 ns unit min max min max cypress parameter alt t ace t elqv chip enable access time ? 25 ? 45 ns t rc [6] t avav, t eleh read cycle time 25 ? 45 ? ns t aa [7] t avqv address access time ? 25 ? 45 ns t doe t glqv output enable to data valid ? 10 ? 20 ns t oha [7] t axqx output hold after address change 5 ? 5 ? ns t lzce [8] t elqx chip enable to output active 5 ? 5 ? ns t hzce [8] t ehqz chip disable to output inactive ? 10 ? 15 ns t lzoe [8] t glqx output enable to output active 0 ? 0 ? ns t hzoe [8] t ghqz output disable to output inactive ? 10 ? 15 ns t pu [9] t elicch chip enable to power active 0 ? 0 ? ns t pd [9] t ehiccl chip disable to power standby ? 25 ? 45 ns switching waveforms figure 7. sram read cycle 1: address controlled [6, 7] figure 8. sram read cycle 2: ce and oe controlled [6] t rc t aa t oha address dq (data out) data valid address t rc ce t ace t lzce t pd t hzce oe t doe t lzoe t hzoe data valid active standby t pu dq (data out) icc notes 6. we and hsb must be high during sram read cycles. 7. device is continuously selected with ce and oe both low. 8. measured 200 mv from steady state output voltage. 9. these parameters are guaranteed by design and are not tested. not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 10 of 17 sram write cycle parameter description 25 ns 45 ns unit min max min max cypress parameter alt t wc t avav write cycle time 25 ? 45 ? ns t pwe t wlwh, t wleh write pulse width 20 ? 30 ? ns t sce t elwh, t eleh chip enable to end of write 20 ? 30 ? ns t sd t dvwh, t dveh data setup to end of write 10 ? 15 ? ns t hd t whdx, t ehdx data hold after end of write 0 ? 0 ? ns t aw t avwh, t aveh address setup to end of write 20 ? 30 ? ns t sa t avwl, t avel address setup to start of write 0 ? 0 ? ns t ha t whax, t ehax address hold after end of write 0 ? 0 ? ns t hzwe [10, 11] t wlqz write enable to output disable ? 10 ? 14 ns t lzwe [10] t whqx output active after end of write 5 ? 5 ? ns switching waveforms figure 9. sram write cycle 1: we controlled [12, 13] figure 10. sram write cycle 2: ce controlled [12, 13] t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid notes 10. measured 200 mv from steady state output voltage. 11. if we is low when ce goes low, the outputs remain in the high impedance state. 12. hsb must be high during sram write cycles. 13. ce or we must be greater than v ih during address transitions. not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 11 of 17 autostore or power up recall parameter alt description stk22c48 unit min max t hrecall [14] t restore power up recall duration ? 550 ? s t store [15, 16] t hlhz store cycle duration ? 10 ms t delay [17] t hlqz , t blqz time allowed to complete sram cycle 1 ? ? s v switch low voltage trigger level 4.0 4.5 v v reset low voltage reset level ? 3.6 v t vsbl [18] low voltage trigger (v switch ) to hsb low ? 300 ns switching waveform figure 11. autostore/power up recall we notes 14. t hrecall starts from the time v cc rises above v switch . 15. ce and oe low and we high for output behavior. 16. hsb is asserted low for 1us when v cap drops through v switch . if an sram write has not taken place since the last nonvolatile cycle, hsb is released and no store takes place. 17. ce and oe low for output behavior. 18. hsb must be high during sram write cycles. not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 12 of 17 hardware store cycle parameter alt description stk22c48 unit min max t dhsb [19, 20] t recover, t hhqx hardware store high to inhibit off ? 700 ns t phsb t hlhx hardware store pulse width 15 ? ns t hlbl hardware store low to store busy ? 300 ns switching waveform figure 12. hardware store cycle notes 19. ce and oe low and we high for output behavior. 20. t dhsb is only applicable after t store is complete. not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 13 of 17 ordering code definitions ordering information these parts are not recommended for new designs. they are in production to support ongoing production programs only. speed (ns) ordering code package diagram package type operating range 25 stk22c48-nf25itr 51-85026 28-pin soic (300 mil) industrial stk22c48-nf25i 51-85026 28-pin soic (300 mil) stk22c48-sf25itr 51-85058 28-pin soic (330 mil) stk22c48-sf25i 51-85058 28-pin soic (330 mil) 45 STK22C48-NF45tr 51-85026 28-pin soic (300 mil) commercial STK22C48-NF45 51-85026 28-pin soic (300 mil) all parts are pb-free. the above table contains final information . please contact your local cypress sales representative for a vailability of these parts packaging option: tr = tape and reel blank = tube speed: 25 - 25 ns 45 - 45 ns package: s = plastic 28-pin 330 mil soic stk22c48 - n f 45 i tr temperature range: blank - commercial (0 c to 70 c) n = plastic 28-pin 300 mil soic lead finish f = 100% sn (matte tin) i - industrial (-40 c to 85 c) not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 14 of 17 package diagrams figure 13. 28-pin (300 mil) soic (51-85026) figure 14. 28-pin (330 mil) soic (51-85058) 51-85026 *f 51-85058 *c not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 15 of 17 document conventions acronyms units of measure acronym description cmos complementary metal oxide semiconductor eia electronic industries alliance i/o input/output nvsram nonvolatile static random access memory rohs restriction of hazardous substances soic small outline integrated circuit symbol unit of measure kb 1024 bits c degree celsius hz hertz k? kilo ohms mhz megahertz ? a microamperes ? f microfarads ? s microseconds ma milliamperes ms milliseconds ns nanoseconds ? ohms pf picofarads v volts w watts not recommended for new designs. in production to support ongoing production programs only.
stk22c48 document number: 001-51000 rev. *e page 16 of 17 document history page document title: stk22c48 16-kbit (2 k 8) autostore? nvsram document number: 001-51000 rev. ecn no. orig. of change submission date description of change ** 2625139 gvch/pyrs 01/30/2009 new data sheet *a 2826441 gvch 12/11/2009 added following text in the ordering information section: ?these parts are not recommended for new designs. in production to support ongoing production programs only.? added watermark in pdf stating ?not recommended for new designs. in production to support ongoing production programs only.? added contents on page 2. *b 3037216 gvch 09/23/2010 added pin configurations and pin definitions table. updated package diagrams . added acronyms and units units of measure table. minor edits. *c 3054310 gvch/keer 10/11/2010 removed inactive parts - stk22c48-nf25, stk22c48-nf25tr, stk22c48-sf25, stk22c48-sf25tr, stk22c48-sf45, stk22c48-sf45tr, STK22C48-NF45i , STK22C48-NF45itr from order- ing information table. updated package diagrams. *d 3189527 gvch 03/07/2011 added watermark in pdf stating ?not recommended for new designs. in production to support ongoing production programs only.? *e 3531563 gvch 02/23/2012 package diagrams : updated 28-pin (330 mil) soic package diagram not recommended for new designs. in production to support ongoing production programs only.
document number: 001-51000 rev. *e revised february 23, 2012 page 17 of 17 all products and company names mentioned in this document may be the trademarks of their respective holders. stk22c48 ? cypress semiconductor corporation, 2006-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 not recommended for new designs. in production to support ongoing production programs only.

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